1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to a phase detector for aligning a reference clock signal and a feedback clock signal.
2. Background Information
Synchronous digital systems, including board-level systems and chip-level systems, rely on one or more clock signals to synchronize elements across the system. Typically, one or more clock signals are distributed across the system on one or more clock lines. However, due to various problems such as clock buffer delays, high capacitance of heavily loaded clock lines, and propagation delays, the rising edges of a clock signal in different parts of the system may not be synchronized. The time difference between a rising (or falling) edge in one part of the system with the corresponding rising (or falling) edge in another part of the system is referred to as “clock skew”.
Clock skew can cause digital systems to malfunction. For example, it is common for circuits in digital systems to have a first flip-flop output driving a second flip-flop input. With a synchronized clock on the clock input of both flip-flops, the data in the first flip-flop is successfully clocked into the second flip-flop. However, if the active edge on the second flip flop is delayed by clock skew, the second flip-flop might not capture the data from the first flip-flop before the first flip-flop changes state.
In particular, it can be difficult to synchronize a reference clock signal and feedback clock signal in such chip-level systems. For example, to synchronize or otherwise align such clock signals, a delay line can be incremented tap-by-tap until the reference clock signal is aligned with the feedback clock signal. Once the appropriate delay is determined for synchronizing or otherwise aligning the clock signals, the delay can be locked. However, such clock signal alignment mechanisms are complex.